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AL103 Revision 1.0 8 PORT LOW COST 10/100 SWITCH
* * * * * * * * * * * Supports 8 10/100 Mbit/s MII ports Capable of trunking up to 800 Mbit/s link Trunk fail-over feature Full- and half-duplex mode operation Speed auto-negotiation through MDIO Built-in storage of 1K MAC addresses Design to utilize low-cost SGRAM Serial EEPROM interface for low-cost system configuration Automatic source address learning Secure mode traffic filtering Broadcast storm control * * * * * * * * Port monitoring support IEEE 802.3x flow control for full-duplex operation Optional backpressure flow control support for half-duplex operation Supports store-and-forward mode switching VLAN support AL102A pin compatible 3.3V operation Packaged in 256-pin PQFP
Product Description The AL103 is an eight-port 10/100 Mbit/s dual speed Ethernet switch. A low-cost Fast Ethernet switch can be implemented using the AL103 with low-cost SGRAM. The AL103 also supports VLAN and multiple port aggregation trunks.
10/100 MAC
Switch Controller
Buffer Manager
10/100 MAC
10/100 MAC High Speed Switch Fabric
Address Control
10/100 MAC
10/100 MAC
Address Table
10/100 MAC EEPROM Interface
10/100 MAC
10/100 MAC
Figure 1
System Block Diagram
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AL103 Revision 1.0
This document contains proprietary information which shall not be reproduced, transferred to other documents, or used for any other purpose without the prior written consent of Allayer Communications.
Disclaimer Allayer Communications reserves the right to make changes, without notice, in the product(s) described or information contained herein in order to improve the design and/or performance. Allayer Communications assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent or copyright to these products, and makes no representations or warranties that these products are free from patent or copyright infringement unless otherwise specified.
Life Support Applications Allayer Communications products are not designed for use in life support appliances, systems, or devices where malfunctions can be reasonably expected to result in personal injury.
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Table of Contents
1. 2. 3. AL103 Overview ..................................................................................................... 5 Pin Descriptions....................................................................................................... 7 Functional Description........................................................................................... 16 3.1 Data Reception............................................................................................... 16 3.1.1 3.1.2 3.1.3 3.1.4 3.2 3.2.1 3.2.2 3.2.3 3.3 3.4 3.5 3.6 3.7 Illegal Frame Length.............................................................................. 16 Long Frames .......................................................................................... 16 False Carrier Events ............................................................................... 16 Frame Filtering....................................................................................... 16 Broadcast Storm Control........................................................................ 17 Frame Transmission............................................................................... 18 Frame Generation................................................................................... 18
Frame Forwarding.......................................................................................... 17
Half Duplex Mode Operation ........................................................................ 18 Secure Mode Operation ................................................................................. 18 Address Learning ........................................................................................... 19 3.5.1 Address Aging........................................................................................ 19 VLAN Support............................................................................................... 19 Port Aggregation (Trunking).......................................................................... 21 3.7.1 3.7.2 3.7.3 3.7.4 3.7.5 Load Balancing ...................................................................................... 21 Trunk Fail Over...................................................................................... 21 Trunk Port Assignment .......................................................................... 22 Port Based Trunk Load Balancing ......................................................... 22 MAC Based Load Balancing ................................................................. 24 Half Duplex Flow Control (Backpressure) ............................................ 25 Full Duplex Flow Control (802.3x) ....................................................... 26
3.8
Flow Control .................................................................................................. 25 3.8.1 3.8.2
3.9 3.10 3.11 3.12 3.13
Queue Management ....................................................................................... 26 Uplink Port..................................................................................................... 27 Port Monitoring.............................................................................................. 27 Media Independent Interface (MII) ............................................................... 28 PHY Management.......................................................................................... 28 PHY Management MDIO ...................................................................... 28
3.13.1
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3.13.2 3.13.3 3.13.4 3.13.5 3.14 3.14.1 3.14.2 3.14.3 3.14.4 3.14.5 3.14.6 3.15 4. 5. 6. 7. 8. 9. 10.
PHY Management Master Mode ........................................................... 28 PHY Management Slave Mode.............................................................. 28 Non Auto-negotiation Mode .................................................................. 29 Other PHY Options................................................................................ 29 System Initialization .............................................................................. 29 Start and Stop Bit ................................................................................... 30 Write Cycle Operation ........................................................................... 30 Read Cycle Operation ............................................................................ 31 Reprogramming the EEPROM Configuration....................................... 31 EEPROM Map ....................................................................................... 32
EEPROM Interface ........................................................................................ 29
SGRAM Interface .......................................................................................... 36
Register Description .............................................................................................. 36 Timing Requirements............................................................................................. 51 Electrical Specifications ........................................................................................ 59 AL103 Mechanical Data........................................................................................ 60 Appendix I (VLAN Mapping Worksheet) ............................................................. 61 Appendix II (Port to Trunk Port Assignment Work Sheet) ................................... 62 Appendix III (Suggested Memory Components)................................................... 63
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1. AL103 Overview
The AL103 provides eight 10/100 Mbit/s Ethernet ports. Each port supports both 10 and 100 Mbit/s data rate. The operation mode is auto-negotiated by the PHY. All ports are full-duplex capable. The device also supports VLAN for workgroup and segment switching applications. The AL103 also supports trunking applications. The chip provides two optional load-balancing schemes, explicit and dynamic. With trunking, it is possible to group up to four full-duplex links together to form a single 800 Mbit/s link. Data received from the MAC interface is stored in the external memory buffer. The AL103 utilizes cost effective SGRAM to provide 8-Mbit or 16-Mbit of buffer memory. During transmission, the data is obtained from the buffer memory and routed to the destination port's output buffer. If a collision occurs in half-duplex operation, the MAC control will back off and retransmit in accordance to the IEEE 802.3 specification. The AL103 provides two flow control methods. For half-duplex operations, an optional jamming based flow control (known as backpressure) is available to prevent loss of data. With this method of flow control, the switch will generate a jam signal when the receive buffer is full and the sending station will not start to transmit until the line is clear. In the full-duplex mode, the AL103 utilizes IEEE 802.3x as the flow control mechanism. All ports support multiple MAC addresses. The switch chip supports 1K MAC addresses internally. These MAC addresses are shared among all eight ports. The initialization and configuration of the switch is programmed by an external EEPROM. Field reconfiguration can be achieved by using a parallel interface to reprogram the EEPROM. The AL103 also supports port based VLAN. The VLAN register set is used to configure the destination ports for multicast and broadcast frames. The device also provides two levels of security for intrusion protection. Security can be implemented on a per port basis. The AL103 operates only in the store and forward mode. The entire frame is checked for error and any frames with errors are automatically filtered and will not be forwarded to the destination port. The AL103 also features port monitoring and broadcast storm throttling.
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Pin Diagram
NC PBANC_8 NC EECLK EEDIO PBCS# PBCAS# PBWE# GND SYSCLK Vcc PBRAS# PBA9_10 PBA0 PBA1 PBA2 PBA3 Vcc PBA4 PBA5 PBA6 PBA7 PBA8_9 PBD0 GND PBD1 PBD2 PBD3 PBD4 PBD5 PBD6 PBD7 Vcc PBD16 PBD17 PBD18 PBD19 PBD20 PBD21 GND PBD22 PBD23 PBD8 PBD9 PBD10 PBD11 PBD12 PBD13 GND PBD14 PBD15 GND PBD24 PBD25 Vcc PBD26 PBD27 PBD28 PBD29 PBD30 PBD31 PBCLKI NC NC
193 1 250 245 240 235 230 225 220 215 210 205 200
NC NC M0CRS GND M0COL GND M0TXD3 M0TXD2 M0TXD1 Vcc M0TXD0 M0TXEN M0TXCLK M0RXER M0RXCLK M0RXDV M0RXD0 M0RXD1 M0RXD2 GND M0RXD3 GND GND GND M1CRS Vcc M1COL Vcc M1TXD3 M1TXD2 M1TXD1 Vcc M1TXD0 M1TXEN M1TXCLK M1RXER M1RXCLK M1RXDV M1RXD0 M1RXD1 M1RXD2 GND M1RXD3 GND Vcc M2CRS GND M2COL GND M2TXD3 M2TXD2 M2TXD1 Vcc M2TXD0 M2TXEN M2TXCLK M2RXER M2RXCLK M2RXDV M2RXD0 M2RXD1 NC NC NC
195
190 5 Pin 1 I.D.
185 10 180 15 175 20 170 25 165 30 160 35 155 40 150 45 145 50 140 55 135 60 130
NC NC Vcc GND M7RXD3 GND M7RXD2 M7RXD1 M7RXD0 M7RXDV M7RXCLK M7RXER M7TXCLK M7TXEN M7TXD0 Vcc M7TXD1 M7TXD2 M7TXD3 Vcc M7COL Vcc M7CRS Vcc GND GND M6RXD3 GND M6RXD2 M6RXD1 M6RXD0 M6RXDV M6RXCLK M6RXER M6TXCLK M6TXEN M6TXD0 Vcc M6TXD1 M6TXD2 M6TXD3 Vcc M6COL Vcc M6CRS Vcc GND M5RXD3 GND M5RXD2 M5RXD1 M5RXD0 M5RXDV M5RXCLK M5RXER M5TXCLK M5TXEN M5TXD0 VccM M5TXD1 M5TXD2 M5TXD3 NC NC
100
105
110
115
120
125
70
75
80
85
90
95
129 65
NC NC M2RXD2 GND M2RXD3 GND Vcc Vcc M3CRS GND M3COL GND M3TXD3 M3TXD2 M3TXD1 GND M3TXD0 M3TXEN M3TXCLK M3RXER M3RXCLK M3RXDV M3RXD0 M3RXD1 M3RXD2 Vcc M3RXD3 Vcc MDC MDIO DEVID0 DEVID1 RESET# TESTMODE EPBYPASS GND M4CRS GND M4COL GND M4TXD3 M4TXD2 M4TXD1 Vcc M4TXD0 M4TXEN M4TXCLK M4RXER M4RXCLK M4RXDV M4RXD0 M4RXD1 M4RXD2 GND M4RXD3 GND Vcc GND M5CRS Vcc M5COL Vcc NC NC
Figure 2
AL103 Pin Diagram (Top View)
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2. Pin Descriptions
Table 1: MII Interface Port 0
PIN NAME M0TXD3 M0TXD2 M0TXD1 M0TXD0 M0TXEN M0TXCLK M0RXD3 M0RXD2 M0RXD1 M0RXD0 M0RXDV M0RXCLK M0RXER M0CRS M0COL PIN NUMBER 7 8 9 11 12 13 21 19 18 17 16 15 14 3 5 I/O O DESCRIPTION Transmit Data - NRZ data to be transmitted to transceiver. Signal TX_EN and TXD0 through TX_D3 are clocked out by the rising edge of TX_CLK. Transmit Enable. Synchronous to the transmit clock. Transmit Clock Input. 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s. Receive Data - NRZ data from the transceiver. For MII interface, signal RX_DV, RX_ER and RX_D0 through RX_D3 are sampled by the rising edge of RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
O I I
I I I I I
Table 2: MII Interface Port 1
PIN NAME M1TXD3 M1TXD2 M1TXD1 M1TXD0 M1TXEN M1TXCLK PIN NUMBER 29 30 31 33 34 35 I/O O DESCRIPTION Transmit Data - NRZ data to be transmitted to transceiver. Signal TX_EN and TXD0 through TX_D3 are clocked out by the rising edge of TX_CLK. Transmit Enable. Synchronous to the transmit clock. Transmit Clock Input. 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s.
O I
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Table 2: MII Interface Port 1 (Continued)
M1RXD3 M1RXD2 M1RXD1 M1RXD0 M1RXDV M1RXCLK M1RXER M1CRS M1COL 43 41 40 39 38 37 36 25 27 I Receive Data - NRZ data from the transceiver. For MII interface, signal RX_DV, RX_ER and RX_D0 through RX_D3 are sampled by the rising edge of RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
I I I I I
Table 3: MII Interface Port 2
PIN NAME M2TXD3 M2TXD2 M2TXD1 M2TXD0 M2TXEN M2TXCLK M2RXD3 M2RXD2 M2RXD1 M2RXD0 M2RXDV M2RXCLK M2RXER M2CRS M2COL PIN NUMBER 50 51 52 54 55 56 69 67 61 60 59 58 57 46 48 I/O O DESCRIPTION Transmit Data - NRZ data to be transmitted to transceiver. Signal TX_EN and TXD0 through TX_D3 are clocked out by the rising edge of TX_CLK. Transmit Enable. Synchronous to the transmit clock. Transmit Clock Input. 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s. Receive Data - NRZ data from the transceiver. For MII interface, signal RX_DV, RX_ER and RX_D0 through RX_D3 are sampled by the rising edge of RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
O I I
I I I I I
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Table 4: MII Interface Port 3
PIN NAME M3TXD3 M3TXD2 M3TXD1 M3TXD0 M3TXEN M3TXCLK M3RXD3 M3RXD2 M3RXD1 M3RXD0 M3RXDV M3RXCLK M3RXER M3CRS M3COL PIN NUMBER 77 78 79 81 82 83 91 89 88 87 86 85 84 73 75 I/O O DESCRIPTION Transmit Data - NRZ data to be transmitted to transceiver. Signal TX_EN and TXD0 through TX_D3 are clocked out by the rising edge of TX_CLK. Transmit Enable. Synchronous to the transmit clock. Transmit Clock Input. 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s. Receive Data - NRZ data from the transceiver. For MII interface, signal RX_DV, RX_ER and RX_D0 through RX_D3 are sampled by the rising edge of RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
O I I
I I I I I
Table 5: MII Interface Port 4
PIN NAME M4TXD3 M4TXD2 M4TXD1 M4TXD0 M4TXEN M4TXCLK M4RXD3 M4RXD2 M4RXD1 M4RXD0 M4RXDV PIN NUMBER 105 106 107 109 110 111 119 117 116 115 114 I/O O DESCRIPTION Transmit Data - NRZ data to be transmitted to transceiver. Signal TX_EN and TXD0 through TX_D3 are clocked out by the rising edge of TX_CLK. Transmit Enable. Synchronous to the transmit clock. Transmit Clock Input. 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s. Receive Data - NRZ data from the transceiver. For MII interface, signal RX_DV, RX_ER and RX_D0 through RX_D3 are sampled by the rising edge of RX_CLK. Receive Data Valid.
O I I
I
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Table 5: MII Interface Port 4 (Continued)
M4RXCLK M4RXER M4CRS M4COL 113 112 101 103 I I I I Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
Table 6: MII Interface Port 5
PIN NAME M5TXD3 M5TXD2 M5TXD1 M5TXD0 M5TXEN M5TXCLK M5RXD3 M5RXD2 M5RXD1 M5RXD0 M5RXDV M5RXCLK M5RXER M5CRS M5COL PIN NUMBER 131 132 133 135 136 137 145 143 142 141 140 139 138 123 125 I/O O DESCRIPTION Transmit Data - NRZ data to be transmitted to transceiver. Signal TX_EN and TXD0 through TX_D3 are clocked out by the rising edge of TX_CLK. Transmit Enable. Synchronous to the transmit clock. Transmit Clock Input. 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s. Receive Data - NRZ data from the transceiver. For MII interface, signal RX_DV, RX_ER and RX_D0 through RX_D3 are sampled by the rising edge of RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
O I I
I I I I I
Table 7: MII Interface Port 6
PIN NAME M6TXD3 M6TXD2 M6TXD1 M6TXD0 M6TXEN PIN NUMBER 152 153 154 156 157 I/O O DESCRIPTION Transmit Data - NRZ data to be transmitted to transceiver. Signal TX_EN and TXD0 through TX_D3 are clocked out by the rising edge of TX_CLK. Transmit Enable. Synchronous to the transmit clock.
O
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Table 7: MII Interface Port 6 (Continued)
M6TXCLK M6RXD3 M6RXD2 M6RXD1 M6RXD0 M6RXDV M6RXCLK M6RXER M6CRS M6COL 158 166 164 163 162 161 160 159 148 150 I I Transmit Clock Input. 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s. Receive Data - NRZ data from the transceiver. For MII interface, signal RX_DV, RX_ER and RX_D0 through RX_D3 are sampled by the rising edge of RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
I I I I I
Table 8: MII Interface Port 7
PIN NAME M7TXD3 M7TXD2 M7TXD1 M7TXD0 M7TXEN M7TXCLK M7RXD3 M7RXD2 M7RXD1 M7RXD0 M7RXDV M7RXCLK M7RXER M7CRS M7COL PIN NUMBER 174 175 176 178 179 180 188 186 185 184 183 182 181 170 172 I/O O DESCRIPTION Transmit Data - NRZ data to be transmitted to transceiver. Signal TX_EN and TXD0 through TX_D3 are clocked out by the rising edge of TX_CLK. Transmit Enable. Synchronous to the transmit clock. Transmit Clock Input. 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s. Receive Data - NRZ data from the transceiver. For MII interface, signal RX_DV, RX_ER and RX_D0 through RX_D3 are sampled by the rising edge of RX_CLK. Receive Data Valid. Receive Clock. Receive Data Error. Carrier Sense. Collision Detect.
O I I
I I I I I
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Table 9: SGRAM Interface
PIN NAME PBD31 PBD30 PBD29 PBD28 PBD27 PBD26 PBD25 PBD24 PBD23 PBD22 PBD21 PBD20 PBD19 PBD18 PBD17 PBD16 PBD15 PBD14 PBD13 PBD12 PBD11 PBD10 PBD9 PBD8 PBD7 PBD6 PBD5 PBD4 PBD3 PBD2 PBD1 PBD0 PBA9_10 PBA8_9 PBANC_8 PIN NUMBER 196 197 198 199 200 201 203 204 215 216 218 219 220 221 222 223 206 207 209 210 211 212 213 214 225 226 227 228 229 230 231 233 244 234 255 I/O DESCRIPTION
I/O
SGRAM Data Bus.
O O O
SGRAM Address. For 16 Mbit/s SGRAM, this pin is PBA10 and for 8 Mbit/s SGRAM this pin is PBA 9. SGRAM Address. For 16 Mbit/s SGRAM, this pin is PBA9 and for 8 Mbit/s SGRAM this pin is PBA 8. SGRAM Address. For 16 Mbit/s SGRAM, this pin is PBA8 and for 8 Mbit/s SGRAM when this pin is not connected.
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Table 9: SGRAM Interface (Continued)
PBA7 PBA6 PBA5 PBA4 PBA3 PBA2 PBA1 PBA0 PBCS# PBRAS# PBCAS# PBWE# PBCLKI 235 236 237 238 240 241 242 243 251 245 250 249 195 O SGRAM address line PBA0- PBA8 are sampled during the ACTIVE command (row address) and READ/WRITE command (column address with PBA8 defining auto precharge).
O O O O O
Chip Select. Enables and disables the command decoder of the SGRAM. SGRAM Row Address Strobe. SGRAM Column Address Strobe. Write Enable. System Clock Output to Drive the SGRAM.
Table 10: EEPROM Interface
PIN NAME EEDIO EECLK PIN NUMBER 252 253 I/O I/O O DESCRIPTION EEPROM Serial Data Input and Output. EEPROM Serial Clock.
Table 11: MII PHY Management Interface
PIN NAME MDC MDIO PIN NUMBER 93 94 I/O O I/O DESCRIPTION PHY Management Clock. PHY Management Data Input and Output.
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Table 12: Miscellaneous Pins
PIN NAME DEVID0 DEVID1 RESET# TESTMODE EPBYPASS PIN NUMBER 95 96 97 98 99 I/O I DESCRIPTION Device ID Number. For AL103, both pins should be connected to ground. Reset Test Mode Pin. This pin should be grounded for normal operation. This pin bypasses the EEPROM setup. This pin should be tied to ground. 80 MHz System Clock. No Connect.
I I I
SYSCLK NC
247 1, 2, 62, 63, 64, 65, 66, 127, 128, 129, 130, 191, 192, 193, 194, 254, 256
I --
Table 13: Power Interface
PIN NAME GND PIN NUMBER 4, 6, 20, 22, 23, 24, 42, 44, 47, 49, 68, 70, 74, 76, 80, 100, 102, 104, 118, 120, 122, 144, 146, 165, 167, 168, 187, 189, 205, 208, 217, 232, 248 10, 26, 28, 32, 45, 53, 71, 72, 90, 92, 108, 121, 124, 126, 147, 149, 151, 155, 169, 171, 173, 177, 190, 202, 224, 239, 246 134 Ground DESCRIPTION
Vcc (3.3V)
3.3V Supply Voltage.
VccM
Supply Voltage for MII Interface. VccM = 5V (5V MII interface) VccM = 3.3V (3.3V MII interface)
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MXTXD3 MXTXD2 MXTXD1 MXTXD0 MXTXEN MXTXCLK MXRXD3 MXRXD2 MXRXD1 MXRXD0 MXRXDV MXRXCLK MXRXER MXCRS MXCOL 32 PBD[n] 9 PBA[n] PBBA PBCS PBRAS PBCAS PBWE PBDSF PBDQM PBCLK
10/100 MAC 10/100 MAC 10/100 MAC 10/100 MAC 10/100 MAC 10/100 MAC 10/100 MAC 10/100 MAC High Speed Switch Fabric
Switch Controller
Address Control
Address Table Buffer Manager PHY Management Management Information EEPROM Interface EEDIO EECLK MDIO MDC
RESET
Figure 3
AL103 Interface Block Diagram
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3. Functional Description
3.1 Data Reception
The port will go into the receive-state when RX_DV in the MII interface is asserted. The MII (Media Independent Interface) presents the received data in four-bit nibbles that are synchronous to the receive clock (25 MHz for 100 Mbit/s or 2.5 MHz for 10 Mbit/s). The AL103 will then attempt to detect the occurrence of the SFD (Start Frame Delimiter) pattern "10101011." All preamble data prior to SFD are discarded. Once SFD is detected from the MII interface, the frame data is forwarded and stored in the buffer of the switch. 3.1.1 Illegal Frame Length During the receiving process, the AL103 MAC will monitor the length of the received frame. Legal Ethernet frames should have a length of no less than 64 bytes and no more than 1536 bytes. Any frames with illegal frame length are discarded. 3.1.2 Long Frames The AL103 can handle frame size up to 1536 bytes. All frames longer than 1536 bytes will be discarded. If the port continues to receive data after the 1536th byte, the port's data will be filtered. If the port is in half-duplex mode, the port will no longer be able to transmit or receive data during the long frame reception. 3.1.3 False Carrier Events If CRS (Carrier Sense) signal in the MII interface is asserted but the receive RX_DV (Receive Data Valid) signal is not asserted within 16BT (Bit Period), the port is considered to have a false carrier event. 3.1.4 Frame Filtering The AL103 will make filtering and forwarding decisions for each frame received based on its frame routing table, VLAN Mapping, port state, and the system configuration. Under the following conditions, received frames are filtered: * The AL103 will check all received frames for errors such as symbol error, FCS error, short event, runt, long event, etc. Frames with any kind of error will not be forwarded to their destination port. Any frame heading to its own source port will be filtered. Frames heading to a disabled receiving port will be filtered. If the input buffer of the port is full, the incoming frame will be discarded. It is recommended that the flow control be used to prevent any loss of data. If the flow control option is enabled, this event will not occur. The remote station will transmit frame when the input buffer becomes available. If the frame has any security violation and the security option is enabled at the receiving port.
* * *
*
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3.2 Frame Forwarding
After a frame is received, both source address (SA) and destination address (DA) are retrieved. The SA is used to update the port's address table and the DA is used to determine the frames destination port. The Address Lookup Engine will attempt to match the destination address with the addresses stored in the address table. If there is a match found, a link between the source port and the destination port is then established. If the first bit of the destination address is "0," the frame is regarded as an unicast frame. The destination address is passed to the Address Lookup Engine, which returns a matched destination port number to identify which port the frame should be forwarded to. If the destination port is within the same VLAN of the receiving port, the frame will be forwarded. If the destination port does not belong to the VLANs specified at the receiving ports, the frame will be discarded. The event will be recorded as a VLAN boundary violation. There are two ways that the AL103 handles frames with unknown destinations. The forwarding decision is controlled by the Flood Control option (System Configuration Register 00). If Flood Control is disabled, the frame will be forwarded to all ports (except the receiving port) within the same VLANs of the receiving port. If the Flood Control option is enabled, the AL103 will forward the frame only to the uplink port specified at the receiving port. Note: The AL103 defines a port as either a single port or a trunk. If the port monitoring function is enabled, the frame forwarding decision is also subject to the port monitoring configurations. If the first bit of the destination address is a "1," the frame will be handled as a multicast or broadcast frame. The AL103 does not differentiate multicast frames from broadcast frames except for the reserved bridge management group address, as specified in table 3.5 of IEEE 802.1d standard. The destination ports of the broadcast frame are all ports within the same VLAN except the source port itself. 3.2.1 Broadcast Storm Control One of the unique features provided by the AL103 is Broadcast Storm Control. This option allows the user to limit the number of broadcast frames into the switch. This option can be implemented on a per port basis. A threshold number of broadcast frames can be programmed in System Register II (register 01). When Storm Control is enabled and the number of cumulated non-unicast frames is over the programmed threshold, the broadcast frame is discarded. If Storm Control is disabled, or the number of non-unicast frames received is not over the programmed threshold, the AL103 will forward the frame to all ports (except the receiving port) specified within the VLANs at the receiving port. If Broadcast-Storm-drop (BConly_SC) is enabled in System Register III (register 02), the AL103 will only drop broadcast frames but not the multicast frames.
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3.2.2 Frame Transmission The AL103 transmits all frames in accordance to IEEE 802.3 standard. The AL103 will send the frames with a guaranteed minimum IPG (Inter Packet/Frame Gap) of 96BT even if the received frames have an IPG less than the minimum requirement. The AL103 also supports transmission of frames with an IPG of 64BT (optional). This option can be selected in System Register III, Bit 8, Register 02. 3.2.3 Frame Generation During a transmit process the frame data is read from the memory buffer and forwarded to the destination port's PHY device in di-bits. Seven bytes of preamble signal (10101010) will be generated first before the SFD (10101011). Frame data is sent after the SFD along with four-bytes of FCS at the end.
3.3 Half Duplex Mode Operation
For half-duplex operation, the MAC logic will abort the transmit-process if collision is detected. Re-transmission of the frame is scheduled in accordance to IEEE 802.3's truncated binary exponential back-off algorithm. If the transmit process has encountered 16 consecutive collisions, an excessive collision error is reported and AL103 will not try to re-transmit the frame unless the retry-on-excessive-collision (REC) option in System Register III (register 02) is enabled. When REC is enabled, the number of collisions are reset to zero and transmission is started as soon as 96 bit time of inter packet gap is passed after the last collision. If a collision is detected after 512 BT of the transmission, a late collision error will be reported but the frame will still be retransmitted after proper back-off time. The AL103 also provides an option for an aggressive back-off in the System Configuration Register II (SuperMAC). This option allows the MAC to back-off only three slots. This will create a more aggressive channel capture behavior than the standard IEEE back-off algorithm.
3.4 Secure Mode Operation
The AL103 provides security support on a per port basis. Whenever the secure mode is enabled, the port will stop learning new addresses. The address table of each port will remain unchanged. In this mode of operation, the address lookup table will freeze and no additional new address will be learned. The AL103 provides two levels of security protection. The most severe intrusion protection is disabling a port if intrusion is experienced. The security management (SecMgmt bit in register 01) will disable a port if a frame with unlearned source address (SA) is received from a secured port (security violation). An alternative is to enable security at the local port level without the security management. When the AL103 is configured this way, the device will only discard frames that have security violations, which prevents intruders from accessing the network.
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3.5 Address Learning
The Table Lookup Engine provides the switching information required to route data frames. The address lookup table is set-up through auto address learning (dynamic) or manual entry (static). The static addresses are assigned to the address table by the EEPROM. All static address entries will not be aged or updated by the AL103. After a frame is received by the AL103, the embedded (SA) and destination address (DA) are retrieved. The source address retrieved from the received frame is automatically stored in a SA buffer. The AL103 will then check for error and security violations, and perform a SA search. If there is no error or security violation, the AL103 will store the source address in the address lookup table. If the SA has been previously stored in another port's SA table, the AL103 will delete the SA from the previously stored location. The Individual MAC Address is a 48-bit unique MAC address to be programmed or learned. Bit 0 of a SA will be masked, i.e. no multicast SA. The AL103 provides an on-chip 1K MAC Address-to-PortID/TrunkID table for the frame destination lookup operations. The AL103 address table contains both static addresses input by the EEPROM and dynamically learned address. It learns the individual MAC addresses from frame received with no errors from the local ports. For received frames that contain a source address learned in another port's address table, that hasn't been aged out, perform the following based on the switches; if the security option is selected for the port, the AL103 considers this a security violation; if port is a non-protected port, the AL103 will delete the SA from the previous port's address table and update it to the current port's address table. However, if the SA is a static address entry, the address will not be updated. 3.5.1 Address Aging A port's MAC address register is cleared on power-up, or hardware reset. If the SA aging option is enabled, the dynamically learned SA will be cleared if it is not refreshed within the programmed time.
3.6 VLAN Support
Each port of the AL103 can be assigned to one or multiple VLANs. Frames from the source port will only be forwarded to destination ports within the same VLAN domain. A broadcast/multicast frame will be forwarded to all ports within the VLAN(s) except the source port itself. A unicast frame will be forwarded to the destination port only if the destination port is in the same VLAN as the source port. Otherwise, the frame will be treated as a frame with unknown DA. If the destination port belongs to the another VLAN, the frame will be discarded and the event will be recorded as a VLAN boundary violation. Each port can be assigned with a dedicated uplink port. Unicast frames with unknown destination addresses will be forwarded to the uplink port of the source port. An uplink port can be either a single port or a trunk. The AL103 provides one VLAN register per ports (register 1E to 2C) for mapping to 8-ports (8bits). Each register contains an 8-bit map to indicate the VLAN group for the port.
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The VLAN registers hold a broadcast destination mask for each source port. The value "1" will indicate the broadcast frames will be routed from the source port to the specified port. Note that the source port bit must be set to "0" within the source port VLAN, because broadcast frames are not routed to the source port. For setting up VLAN for trunking, please see the following section on trunking for detail. VLAN Set Up Example A VLAN set up worksheet is provided in Appendix I. You can complete the VLAN map easily by simply marking the ports you wish to send broadcast frame to. For example, let's assume we want to set up two VLAN groups in an 8-port switch: Group 1 consists of: 0, 1, 2, 5, and 6. Group 2 consists of: 2, 3, 4, and 7. The completed VLAN bit maps are shown in Table 14.
Table 14: VLAN Map for an 8 Port Switch
PORT 6/REG. 2A PORT 7/REG. 2C 0 0 0 1 1 1 0 0 PORT 0/REG. 1E PORT 1/REG. 20 PORT 2/REG. 22 PORT 3/REG. 24 PORT 4/REG. 26 PORT 5/REG. 28 0 1 0 0 0 1 1 1
PORT
BIT
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
0 1 1 0 0 1 1 0
0 1 1 0 0 1 0 1
1 1 1 1 1 0 1 1
1 0 0 1 0 1 0 0
1 0 0 0 1 1 0 0
0 0 1 0 0 1 1 1
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3.7 Port Aggregation (Trunking)
The AL103 supports trunking/port aggregation. Port aggregation and trunking is essentially a method to treat multiple physical links as a single logical link. The benefit of trunking is the ability to group multiple lower speed links into one higher speed link. For example, four full-duplex 100 Mbps links can be used as one single 800-Mbps link. This is very useful for switch to switch, switch to server, and switch to router applications. The AL103 considers a trunk as a single port entity regardless of the trunk composition. Two to four ports can be grouped together as a single trunk link. The grouping of the ports in the trunk must be from the top four ports or the bottom four ports of the device, i.e. port 0 to 3 or port 4 to 7. In a multiple link trunk, the links within the trunk should have a balanced amount of traffic in order to achieve maximum efficiency. One of the requirements for transmission is that the frames being transmitted must be in order. Therefore, some sort of load balancing among the links of the trunk must be deployed. The AL103 offers two methods of load balancing which can be selected in the System Configuration Register I (register 00). 3.7.1 Load Balancing The two load-balancing methods that AL103 uses to support trunking are port based and MAC address based. Port based load balancing method is an explicit port assignment scheme. It requires each individual port be assigned to a specific link (trunk port) in the trunk. If the port is not assigned, the frame might be routed to the trunk randomly which may cause the frames to go out of order. The port based load balancing trunk can be assigned as a 2-, 3-, or 4-port trunk. During transmission of the frame, it will be routed from the source port to the assigned trunk port. When a frame is received from any one of the trunk ports, it will be routed to the destination port within the VLAN. In essence, the AL103 treats a trunk as any single port within the same VLAN. If the ports traffic is evenly distributed among all the trunk ports, load balancing is achieved and the aggregate bandwidth of the trunk can be as high as 800 Mbit/s (full-duplex). The alternative is the MAC address based load balancing. When the AL103 receives a frame with a trunk destination, it will automatically forward the frame to a port in the trunk based on the source, destination, or the combination of the source and destination MAC address. The MAC address load balancing decision is based on a proprietary algorithm. The MAC address based load-balancing trunk also can be assigned as a 2-, 3-, or 4-port trunk. 3.7.2 Trunk Fail Over If a link is lost in one of the trunk ports, frame loss will occur. The trunk fail-over feature in the AL103 can prevent frame loss caused by link failure in a trunk port. When the trunk fail-over option is enabled in register 2D, bit 9 (L2Fail), the AL103 will automatically shift the load from the port with the lost link to the next available port. This option is available for MAC address based loading trunk only. Once the port with a lost link recovers and links up, the AL103 will return to the original trunk setting.
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3.7.3 Trunk Port Assignment The maximum number of trunks for the AL103 is two. The Port Configuration I registers provide the ability to designate a port to be a member of a trunk. The trunk can consist of up to four trunk ports. A trunk group must consist of either the top four ports or the bottom four ports, for example a trunk can consist of port 0 through port 3 or port 4 through port 7. Each trunk port's number is in sequence of 00, 01, 10, and 11 corresponding to the order of port of the devices. For example, port 1 and 5 are 01 (See Figure 4).
AL103
Ports
0
1
2
3
4
5
6
7
Trunk Port 0
Trunk Port 1
Figure 4
Trunk Port Numbering
3.7.4 Port Based Trunk Load Balancing For port-based load balancing, a trunk port must be assigned to each port for all defined trunks. The port assignment is done by programming Port to Trunk Port Registers (2E to 35). A port assignment worksheet is provided at the back of the data sheet. It is recommended that ports be evenly distributed among all trunk ports to prevent overloading any single trunk port. Port Based Load Balancing Set up Example Note: Register bits are reference by X.Y, where "X" is the register number and "Y" is the bit number. Appendix I and II provide a worksheet for port to trunk port and VLAN assignment. The example is designing an 8-port switch with a 3-port based loading trunk. The desired trunk ports are 5, 6, and 7. We want to assign port 0 to trunk port 5, port 1 and 3 to trunk port 6, and port 2 and 4 to trunk port 7. 1. The Port Configuration I register bits 15.9, 16.9, and 17.9 are set to 1. This assigns ports 5, 6, and 7 as a trunk port. 2. Assign port 0 to trunk port 5, port 1 and 3 to trunk port 6, and port 2 and 4 to trunk port 7. Therefore, set port to trunk port register bits. 2E.2= 0, 2E.3 =1 2F.2= 1, 2F.3 =0 30.2= 1, 30.3 =1 31.2= 1, 31.3 =0 32.2= 1, 32.3 =1
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3. Trunk ports should be assigned with their own port number in the port to trunk Port register. The port to trunk-port bits are as follows: 33.2= 0, 33.3 =1 34.2= 1. 34.3 =0 35.2= 1, 35.3 =1 Set the remaining bits to all zeros in port to trunk port registers. 4. Assigning VLAN. The VLAN map should be assigned as shown. All bits are set to "1" while the bits 1E.6 and 1E.7 are set to "0" because port 0 is assigned to port 5. All the other ports are set up similarly. Bits 15 through 8 are reserved and should be set to `0' for all VLAN mapping registers.
Table 15: VLAN Mapping for Port Based Load Balancing Trunk
PORT 6/REG. 2A PORT 7/REG. 2C 0 0 0 1 1 1 1 1 PORT 0/REG. 1E PORT 1/REG. 20 PORT 2/REG. 22 PORT 3/REG. 24 PORT 4/REG. 26 PORT 5/REG. 28 0 0 0 1 1 1 1 1
PORT
BIT
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
0 0 1 1 1 1 1 0
0 1 0 1 1 1 0 1
1 0 0 1 1 0 1 1
0 1 0 1 0 1 1 1
1 0 0 0 1 1 1 1
0 0 0 1 1 1 1 1
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3.7.5 MAC Based Load Balancing For MAC address based load balancing, there is no need to assign a port to a trunk port. The AL103 dynamically assigns MAC addresses to the trunk port. MAC address based trunks can consist of two, three, or four trunk ports. The bits are chosen for their randomness. The statistically random bits will ensure good load balancing among all trunk-ports. The following is a procedure to set up the MAC based load trunk. 1. Select MAC address load trunking by setting bit 00.3 to "1." 2. Select the trunk ports using Port Configuration Register I bit 9. 3. Assign the ports and the trunk port to the same VLAN using register 1E to 2C. 4. When the number of trunk ports is four, the following steps are not required. If the number of trunk ports are two or three, set register bit 2D.8 (L2MAP) to "1." 5. Set the TrunkMap1 or TrunkMap0 in register bits 7 through 0. These bits indicate the mapping of trunk ports. For example, if ports 0 and 1 are used as trunk ports, then set the bits 2D.0 and 2D.1 to "1." If ports 5 and 7 are used as trunk ports, set bits 2D.5 and 2D.7. The trunk port mapping and the trunk member bits set in Port Configuration I register must match. 6. Finally, select the algorithm for MAC based loading. Set register 2D.10 to "1" for source address only, and "0" for the combination of source and destination addresses. The port VLAN grouping should include all the trunk ports. Since the AL103 will assign the port by MAC addresses, frames from any single port may be routed to any trunk ports. MAC Based Load Balancing Example The desired trunk port is 4, 5, 6, and 7. Therefore, the port configuration register bits 15.9, 17.9, 19.9, and 1B.9 are set to "1." Select MAC address loading by setting bit 00.3 to "1."
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Table 16: VLAN Mapping for MAC Based Loading Trunk
PORT 0/REG. 1D PORT 7/REG. 2B 0 0 0 0 1 1 1 1 PORT 1/REG. 1F PORT 2/REG. 21 PORT 3/REG. 23 PORT 4/REG. 25 PORT 5/REG. 27 PORT 6/REG. 29 0 0 0 0 1 1 1 1
PORT
BIT
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 0
1 1 1 1 1 1 0 1
1 1 1 1 1 0 1 1
1 1 1 1 0 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
Note: All bits are set to "1" except the ports themselves.
3.8 Flow Control
The AL103 can operate at two different modes, half- and full-duplex. Each port can operate at either full- or half-duplex and can be configured to have flow control enabled or no flow control independently on a per port basis. 3.8.1 Half Duplex Flow Control (Backpressure) If the half-duplex flow control option is elected, backpressure will be used for flow control. Whenever the receive frame buffer of a port is full, the MAC of the port will start sending a JAM signal through the port. The remote station after sensing the JAM signal will defer transmission. Backpressure flow control is applied to ensure that there is no dropped frame. The AL103 supports two types of backpressure, collision based and carrier based. Carrier based backpressure is generated by the AL103, when the switch port's frame buffer is full. The AL103 will cease to jam the line when the port has buffer space available for frame reception. The IPG of the jamming signal can be selected from 48BT, 56BT, 65BT, 72BT, and 96BT. This can be selected in register 02 bits 3 and 2. The BpIPGSelEn bit must be set to 1 to select backpressure IPG less than 96BT. Collision based backpressure is generated by the AL103, only when the switch port receives a frame. The AL103 will cease to jam the line, when the line is idle. The carrier based backpressure has several advantages over collision based backpressure such as:
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* *
Collision based backpressure can cause a late collision. After 16 consecutive collisions, the MAC could drop frames. The AL103 has an option not to drop frame after 16 collisions. However, the end terminal may still drop frames.
Therefore, we recommend the use of carrier based backpressure as the preferred method for halfduplex flow control. In this mode of operation, we also recommend that the IPG of the JAM signal should be set at less than 96BT. This is because if the IPG is at 96 BT, the far end terminal might still be able to transmit the frame and cause a collision. The excessive collision could cause frames to be dropped. The AL103 also supports collision-based backpressure for customers that prefer collision-based backpressure. 3.8.2 Full Duplex Flow Control (802.3x) In the full-duplex mode, the AL103 will transmit and receive the frame in accordance to 802.3x. Note that the transmission channel and the receiving channel operate independently. In the incoming direction, whenever the receive frame buffer of a port is full, the MAC of the port will send out a PAUSE frame with its delay value set to maximum. The PAUSE frame will deter any incoming frame from flowing into the port. After the receive frame buffer is reduced below the backpressure watermark level (register 04, bit 11:10), the MAC of the port will then send out a PAUSE frame with the delay value set to zero to resume receiving the incoming frame flow. In the outgoing direction, whenever a incoming PAUSE frame with a non-zero delay value is received through a port, the MAC of the port will stop the next frame transmission after the ongoing frame transmission is finished. It will start its pause timer and resume frame transmission either after the pause timer expired or when a PAUSE frame with a zero delay value is received. When the 802.3x flow control option is elected, the device will program the appropriate bit in the auto-negotiation capability field. When the AL103 is used in the full-duplex mode, it is recommended that flow control should be turned on which prevents the buffer from overflow and loss of frames. If the connected device has no 802.3x capability, then the recommended link setting is half-duplex.
3.9 Queue Management
The AL103 ports have an advanced queue management algorithm for optimal switching performance. All frames received by AL103 are stored into the shared memory. If the frame is unicast type, the location of the frame in the buffer is then passed to the destination output queue manager. It is up to the Destination Output Queue Manger to extract the frame from the buffer and transmit. If the output queue manager receives more frames than it can send out, it simply stores the locations of the frames and transmits them after transmitting the current frame. There are two ways to manage the output queues. One method is that all eight output queues will share the frame buffer to the shared memory limit, without limit to each individual queue. When this method is chosen by setting bit 00.15 to "0," shared buffer memory is allocated to the incoming frame from any port as long as free buffer is available. When extreme cases of congestion are experienced, such as traffic merging into a single port or speed mismatch for a long period of time, a single output queue may occupy the entire shared buffer causing other ports to drop frames. In
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this case, the flow control option is recommended so when the frame buffer is full, incoming frames will be backpressured. To prevent buffer starvation, half of the memory is reserved and allocated to each port while the other half is shared. The other option is to limit the number of frames that each output queue can store. This option is selected by setting bit 00.15 to "1." An output queue watermark can be set in System Configuration Register I (Register 00, Bits 7:6) to keep the balance between utilization and fairness of buffer sharing. This method prevents other ports from suffering performance reduction due to a single port experiencing an extreme congestion. If severe congestion is experienced in a single port, only that port will suffer from frame loss because the buffer is limited to its dedicated portion. Other ports will not experience any frame loss due to congestion problem in other ports since all other ports retain their own allocated buffer space. When an output queue or multicast queue experiences a buffer full condition, the AL103 will backpressure the incoming frames if flow control is enabled. A watermark for buffer full condition can be selected in register 04.
3.10 Uplink Port
The uplink port provides a means to connect the switch with a repeater hub, a workgroup switch, a router, or any type of interconnecting device compliance with IEEE 802.3 standards. If flood control is enabled, the AL103 will send all frames with unmatched DA and multicast/ broadcast frames to the uplink port. It is very important that each port is assigned to an uplink port via the Port Configuration Register (0D to1C), or data frames might be lost. The uplink port should be configured to be within the same VLAN of the source port. If the uplink port is not a member of the VLANs, the broadcast or multicast frames will not be forwarded to its designated uplink port. Multiple VLANs can share the same uplink port. The AL103 will direct the following frames to the uplink port: * * Frames with a unicast destination address that doesn't match with any MAC address stored in the switch. Frames with a broadcast/multicast destination address if the uplink port is in the same VLAN.
Note: When configuring an uplink port, the uplink port should designate itself as the uplink port.
3.11 Port Monitoring
The AL103 supports port monitoring. This feature provides complete network monitoring capability at 100 Mbit/s. A copy of egress (TX) data and ingress (RX) data of the monitored port is sent to their respective snooping ports. The monitored port is selected by register 30. The AL103 allows transmit and receive data to be monitored by different snooping ports. The snooping ports are also selected by register 30.
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3.12 Media Independent Interface (MII)
The MAC of each port of the AL103 is connected to the PHY through the standard MII interface. For receiving frames, the received data (RXD[3:0]) is sampled at the rising edge of the receive clock (RX_CLK). Assertion of the receive data valid (RX_DV) signal will cause the MAC to look for start of SFD. For transmission, the transmit data enable (TX_EN) signal is asserted when the first preamble nibble is sent on the transmit data (TXD[3:0]) lines. The transmit data is clocked out by the rising edge of the transmit clock (TX_CLK). Prior to any transaction, the AL103 will output 32-bits of "1" as a preamble signal and then after the preamble, a "01" signal is used to indicate the start of the frame.
3.13 PHY Management
The AL103 supports transceiver management through the serial MDIO and MDC signal lines. The device provides two modes of management, master and slave mode. In the master mode of operation, the AL103 controls the operation modes of the link but in the slave mode the PHY controls the operating mode. 3.13.1 PHY Management MDIO For a write operation, the device will send a "01" to signal a write operation. Following the "01" write signal their will be the 5-bit ID address of the PHY device and the 5-bit register address. A "10" turn around signal is then used to avoid contention during a read transaction. After the turn around, the 16-bit of data will be written into the register and then after the completion of the write transaction, the line will be put in a high impedance state. For a read operation, the AL103 will output a"0" to indicate a read operation after the start of the frame indicator. Following the "10" read signal will be the 5-bit ID address of the PHY device and the 5-bit register address. Then, the AL103 will cease driving the MDIO line, and wait for one bit time. During this time, the MDIO should be in a high impedance state. The device will then synchronize with the next bit of "0" driven by the PHY device, and continue to read 16-bit of data from the register. The detail timing requirements on PHY management signals are described in the section "Timing Requirement." 3.13.2 PHY Management Master Mode In the master mode, the AL103 will continuously poll the status of the PHY devices through the serial management interface. The device will also configure the PHY capability fields to ensure proper operation of the link. The configuration of the link is automatic. The link capability is programmed by the AL103 through the port configuration register. The AL103 reads from the standard IEEE PHY registers to determine the auto-negotiated operating speed and mode. If there is a need to manually set the operation mode because of flow control and cabling issues the AL103 can set the port operation mode through the MDIO interface (see EEPROM section for programming the AL103). 3.13.3 PHY Management Slave Mode In the slave mode, the PHY controls the programming of the operating mode. The AL103 will continuously poll the status of the PHY devices through the serial management interface to determine the operation mode of the link.
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This mode of PHY management is very useful for unmanaged switches. The operating mode of the link can be changed by programming the mode pin of the PHY through a jumper. The AL103 also supports 100Base-TX transceivers without a MDIO interface or MII to MII interface. When MDIO is disabled, the AL103 will operate in the operation mode specified in the port configuration register (register 0D to 1C). 3.13.4 Non Auto-negotiation Mode The AL103 can also turn off the auto-negotiation capability of the PHY. When auto-negotiation is turned off, the AL103 is in the slave mode and the transceiver will determine the link's operating mode. 3.13.5 Other PHY Options Some Legacy Fast Ethernet devices and other low cost devices have no auto-negotiation capability. In those cases when the transceiver will not be able to perform auto-negotiation, the switch transceiver will typically do a parallel detection and update the information in the transceiver's register. Unfortunately, such register addresses are vendor specific. The AL103 provides a register (register 05) to specify the register address of the PHY for the AL103 to read. The AL103 will read from that register and configure the port operation accordingly. Register 05 also provides some additional flexibility's for some of the PHYs in the market. In general, the system designer should set the ID of the PHY devices as 0 for port 0, 1 for port 1, and 7 for port 7. Certain PHYs utilize PHY address 00000 as a broadcast address. Bit 1 of the register 05 allows the AL103 to start with PHY address 01000. This provision allows the engineers to work around the PHY's that have problems handling address 00000. Quad PHYs may have 2-port ordering in the chip pinout, both clockwise and counter clockwise. Register 05 bit 2, programs the AL103 port order to go in either direction. This provision enables engineers to easily implement designs with any PHY. There is also a slow MDIO clock (17 KHz) available for PHY that is not capable of handling a high speed MDIO clock. If for some reason, the transceiver is connected to a device and that device fails to auto-negotiate, the AL103 will default the data rate and duplex mode to the default setting in the port configuration register.
3.14 EEPROM Interface
The AL103 provides three functions with the EEPROM interface: system initialization, obtaining system status, and reconfiguring the system in real time. The AL103 uses the 24C02 serial EEPROM device (2048 bits organized as 256 bits x 8). 3.14.1 System Initialization The EEPROM interface is provided so that the manufacturer can provide a pre-configured system to their customers which allows customers to change or reconfigure their system and retain their preferences. The EEPROM contains configuration and initialization information, which will be accessed at power up or reset.
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If the reset pin is held low, the AL103's EEPROM interface will go into a high impedance state. This feature is very useful for reprogramming the EEPROM during installation or reconfiguration. The EEPROM can be reprogrammed by an external parallel port. For reprogramming using a parallel port, a signal is used to hold the RESET pin low. The EEPROM interface will then be in the high-impedance state. An external device can then program the EEPROM through the EEDIO and the EECLK pins. The EEPROM address should be set to 000. 3.14.2 Start and Stop Bit The write cycle is started by a start bit and ended by a stop bit. A start bit is a transition from high to low of EEDIO when EEC is high. The operation terminates when EEDIO goes from low to high when EEC is high. Following a start condition, the writing device must output the address of the EEPROM. The most significant four bit of the EEPROM address is the device type identifier which has an address of 1010. The EEPROM device address should be set to 000.
EECLK
EEDIO
Data or Address Valid
START BIT
Data Change
STOP BIT
Figure 5
EEPROM Start and Stop Bit
3.14.3 Write Cycle Operation The EECLK is an output from the AL103 while EEDIO is a bi-directional signal. When accessing the EEPROM, the reset pin has to be held low or initialization of the AL103 must be finished before a writing operation can begin. A typical write operation is shown in Figure 6.
Device Address
Start
Stop
S
AA
A
8-Bit Word Address
8-Bit Data n
S
Acknowledge
Acknowledge
Acknowledge
Figure 6
EEPROM Write Cycle
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3.14.4 Read Cycle Operation Read operations are initiated in the same manner as write operations, with the exception that the R/ W bit of the EEPROM address is set to a "1."
Device Address Device Address
Start
Start
Stop
S
AA
A
8-Bit Word Address
S
AA
A 8-Bit Data n
S
EEDIO Acknowledge Acknowledge Acknowledge No Acknowledge
Figure 7
EEPROM Read Cycle
3.14.5 Reprogramming the EEPROM Configuration There are two ways that the system can be reconfigured. Figure 8 shows an application using the parallel interface to reprogram the EEPROM. In this application, the parallel port holds the reset pins low, which forces the EEDIO pins to go into high impedance. Once the pins are in high impedance, the EEPROM can now be programmed by the parallel port. Once the parallel port releases the reset pins, the devices will start to download the EEPROM data and reconfigure the devices. An alternate way of reconfiguring the system is to directly change the register settings of the AL103. After initialization, the EEPROM interface can act as a virtual EEPROM. In order for this method to work, the EEPROM's device address must be 000, while the AL103's address will be 100. The customer can now program the AL103 as an EEPROM. The read and write timing is the same as an EEPROM. Because you read as well as write to the AL103, the registers status can be read from the AL103. This will serve as a very useful tool for diagnostic of an unmanaged switch.
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Reset
AL103
EECLK EEDIO
Parallel Port EEPROM
Figure 8
EEPROM Parallel Port
3.14.6 EEPROM Map Table 17 shows the EEPROM address map cross-referenced to the register/bit set of the AL103. Addresses 00 through 6D are for configuring the device. They are downloaded by the AL103 after reset or power up. Since the AL103 registers are 16-bit wide, it takes two EEPROM addresses for each AL103 register. Even numbered EEPROM addresses corresponds to the upper byte of the AL103 registers while the odd numbered EEPROM addresses corresponds to the lower byte of the AL103 registers. Address 06 and 07 should be programmed as 0000 0001 and 0001 0100. The address 6F indicates the last address entry. If no static address is used in the switch, the address 6F should be programmed. Addresses 70 to FF are used for programming the static address entry. The following format is an example of Static Entry 1, Address 70-7F.
Table 17: Static Address Entry Format for EEPROM
EEPROM ADDRESS 70 71 72 73 74 75 76 77 BIT 7 6 5 4 3 2 1 0
Reserved (Must be all zero) Reserved Port ID 000XXX or Trunk ID 100YYY
MAC Address [47:40] MAC Address [39:32] MAC Address[31:24] MAC Address[23:16] MAC Address[15:8] MAC Address[7:0]
Note: XXX represents port ID and YYY represents Trunk ID.
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Table 18: AL103 EEPROM Mapping
EEPROM PHYSICAL ADDRESS 00-01 02-03 04-05 06-07 08-09 0A-0B 0C-0D 0E-0F 10-11 12-13 14-15 16-17 18-19 1A-1B 1C-1D 1E-1F 20-21 22-23 24-25 26-27 28-29 2A-2B 2C-2D 2E-2F 30-31 32-33 34-35 36-37 System Configuration I System Configuration II System Configuration III Reserved (Value must be 0000 0001 0100) Reserved Vendor Specific PHY Port Monitoring Configuration Reserved Reserved Reserved Reserved Reserved Reserved Port 0 Configuration I Port 0 Configuration II Port 1 Configuration I Port 1 Configuration II Port 2 Configuration I Port 2 Configuration II Port 3 Configuration I Port 3 Configuration II Port 4 Configuration I Port 4 Configuration II Port 5 Configuration I Port 5 Configuration II Port 6 Configuration I Port 6 Configuration II Port 7 Configuration I DESCRIPTION
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Table 18: AL103 EEPROM Mapping (Continued)
38-39 3A-3B 3C-3D 3E-3F 40-41 42-43 44-45 46-47 48-49 4A-4B 4C-4D 4E-4F 50-51 52-53 54-55 56-57 58-59 5A-5B 5C-5D 5E-5F 60-61 62-63 64-65 66-67 68-69 6A-6B 6C-6D 6E 6F 70-77 Port 7 Configuration II Reserved (Must be all zero) Port 0 VLAN Map Reserved (Must be all zero) Port 1 VLAN Map Reserved (Must be all zero) Port 2 VLAN Map Reserved (Must be all zero) Port 3 VLAN Map Reserved (Must be all zero) Port 4 VLAN Map Reserved (Must be all zero) Port 5 VLAN Map Reserved (Must be all zero) Port 6 VLAN Map Reserved (Must be all zero) Port 7 VLAN Map Miscellaneous Register Checksum Port 0 to Trunk Port Assignment Port 1 to Trunk Port Assignment Port 2 to Trunk Port Assignment Port 3 to Trunk Port Assignment Port 4 to Trunk Port Assignment Port 5 to Trunk Port Assignment Port 6 to Trunk Port Assignment Port 7 to Trunk Port Assignment Reserved Last Static Entry EEPROM Address (Value must be 6F for no Static Entry) Static Entry 1
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Table 18: AL103 EEPROM Mapping (Continued)
78-7F 80-87 88-8F 90-97 98-9F A0-A7 A8-AF B0-B7 B8-BF C0-C7 C8-CF D0-D7 D8-DF E0-E7 E8-EF F0-F7 F8-FF Static Entry 2 Static Entry 3 Static Entry 4 Static Entry 5 Static Entry 6 Static Entry 7 Static Entry 8 Static Entry 9 Static Entry 10 Static Entry 11 Static Entry 12 Static Entry 13 Static Entry 14 Static Entry 15 Static Entry 16 Static Entry 17 Static Entry 18
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3.15 SGRAM Interface
All ports of the AL103 work in Store-And-Forward mode so that all ports can support both 10 Mbps and 100 Mbps data speed. The AL103 utilizes a central memory buffer pool, which is shared by all ports within the same device. After a frame is received, it is passed across the SGRAM interface and stored in the buffer. During transmit, the frame is retrieved from the buffer pool and forwarded to the destination port. The AL103 is designed to use 8 Mbit SGRAM or 16 Mbit SGRAM to achieve low cost and high performance. The SGRAM is accessed in Page Burst Access Mode for very high-speed access. This burst mode is repeatedly sent to the same column. If burst mode reaches the end of the column address, it then wraps around to the first column address (=0) and continues to count until interrupted by the new read/write, pre-charge, or a burst stop command. The AL103 will initialize the SGRAM automatically and pre-charges all banks and inserts eight auto-refresh commands. It will also program the mode registers for the AL103's read and write operations. SGRAM essentially is a SDRAM. Dynamic memories must be refreshed periodically to prevent data loss. The SGRAM uses refresh address counters to refresh automatically. The SGRAM autorefresh command generates a pre-charge command internally in the SGRAM. The AL103 will insert an auto-refresh command once every 15 microseconds.
4. Register Description
Table 19: Register Tables Summary
REGISTER ID 00 01 02 03 04 05 06-0C 0D 0E 0F 10 REGISTER DESCRIPTION System Configuration I System Configuration II System Configuration III Reserved Testing Register Vendor Specific PHY Status Reserved Port 0 Configuration I Port 0 Configuration II Port 1 Configuration I Port 1 Configuration II REVERSE EEPROM ADDRESS 00,01 02,03 04,05 06,07 08,09 0A,0B 0C-19 1A,1B 1C,1D 1E,1F 20,21
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Table 19: Register Tables Summary (Continued)
11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E Port 2 Configuration I Port 2 Configuration II Port 3 Configuration I Port 3 Configuration II Port 4 Configuration I Port 4 Configuration II Port 5 Configuration I Port 5 Configuration II Port 6 Configuration I Port 6 Configuration II Port 7 Configuration I Port 7 Configuration II Reserved Port 0 VLAN Map Reserved Port 1 VLAN Map Reserved Port 2 VLAN Map Reserved Port 3 VLAN Map Reserved Port 4 VLAN Map Reserved Port 5 VLAN Map Reserved Port 6 VLAN Map Reserved Port 7 VLAN Map Miscellaneous Register Port 0 to Trunk Port Assignment 22,23 24,25 26,27 28,29 2A,2B 2C,2D 2E,2F 30,31 32,33 34,35 36,37 38,39 3A,3B 3C,3D 3E,3F 40,41 42,43 44,45 46,47 48,49 4A,4B 4C,4D 4E,4F 50,51 52,53 54,55 56,57 58,59 5A,5B 5C,5D
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Table 19: Register Tables Summary (Continued)
2F 30 31 32 33 34 35 36-38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 Port 1 to Trunk Port Assignment Port 2 to Trunk Port Assignment Port 3 to Trunk Port Assignment Port 4 to Trunk Port Assignment Port 5 to Trunk Port Assignment Port 6 to Trunk Port Assignment Port 7 to Trunk Port Assignment Reserved System Status Register Port 0 Operation Status Port 1 Operation Status Port 2 Operation Status Port 3 Operation Status Port 4 Operation Status Port 5 Operation Status Port 6 Operation Status Port 7 Operation Status Indirect Resource Access Command Indirect Resource Access Data I Indirect Resource Access Data II Indirect Resource Access Data III Indirect Resource Access Data IV Check Sum 5E,5F 60,61 62,63 64,65 66,67 68,69 6A,6B 6C-71 72,73 74,75 76,77 78,79 7A,7B 7C,7D 7E,7F 80,81 82,83 84,85 86,87 88,89 8A,8B 8C,8D 8E,8F
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System Configuration Register I (Register 00) System Configuration Registers 01 ~ 03 are global system configuration registers. Any options selected in these registers affects the overall system operation.
Table 20: System Configuration Register I (Register 00)
BIT 15 NAME OutQMgmt DESCRIPTION Output Queue Management Method. 0: Output queue is not limited until the frame buffer is full. 1: Output queue is limited to the output queue watermark specified in register 00 bits [7:6]. Flood Control. Control for the forwarding of unicast frames with unknown destination received from the non-uplink ports. 0: Enable. Frames received with unknown unicast destination MAC address will be forwarded to all the ports (excluding the receiving port) within the VLANs specified at the receiving port. 1: Disable. Frames received with unknown unicast destination MAC address will be forwarded to the uplink port specified for the receiving port. Security Enforcement. 0: Auto security off. The security violation at a secured port will not change its port state. 1: Auto security on. The security violation at a secured port will cause the port into DISABLE state. Switch Table Entry Aging Control. 0: Disable. The table aging process will be stopped. 1: Enable. The table aging process will be running to age every dynamically learned table entry. Reserved (Must set to 0000). Port Incoming Frame Flow Monitoring Enable Control. 0: Disable 1: Enable Port Outgoing Frame Flow Monitoring Enable Control. 0: Disable 1: Enable Output Queue Watermark. Watermark selection for output queues and multicast queue full conditions. 16 Mbit/s SGRAM 00:128; 01:512; 10:768; 11:Test Mode. 8 Mbit/s SGRAM 00:64; 01:256; 10:384; 11:Test Mode. Set value to 00.
14
FloodCtl
13
SecMgmt
12
AgeEn
11~10 9
Reserved PInMon
8
POutMon
7~6
OutQWM
5~4
Reserved
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Table 20: System Configuration Register I (Register 00) (Continued)
3 L2Trunk Layer 2 Trunk Loading Method. 0: Port based loading. Trunking decisions will be based on Trunk Port Assignment Registers. 1: MAC address based loading. Trunking decisions will be based on source port MAC addresses. Frame Time Out Enable. 0: Device will not timeout frames based on MaxDelay. 1: Device will timeout frames. Reserved (Must set to 00).
2
TimeoutEN
1~0
Reserved
Table 21: System Configuration Register II (Register 01)
BIT 15~8 7~6 NAME MaxAge MaxDelay DESCRIPTION Maximum Age For Dynamically Learned MAC Entries. 0000 0000: 1 sec. to 1111 1111: 256 sec. Maximum Frame Transition Delay Through The Switch. 00: 1 second. 01: 2 seconds. 10: 3 seconds. 11: 4 seconds. Maximum Number of Broadcast Frames That Can Be Accumulated In Each Input Frame Buffer. 00: 16 frames. 01: 32 frames. 10: 48 frames. 11: 64 frames. 0: Disable. Device will perform the IEEE standard exponential back-off algorithm when a collision occurs. 1: Enable. When collisions occur, the AL103 will back off up to 3 slots. Retry on Excessive Collision. 0: Normal collision handling. 1: Retry transmission after 16 consecutive collisions. Select the Bits Position for MAC Address To Trunk Assignment. 00: Source MAC address [1:0]. 01: Source MAC address [3:2]. 10: Source MAC address [5:4]. 11: Source MAC address [7:6].
5~4
MaxStorm
3
SuperMAC
2
REC
1~0
L2TbitSel
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Table 22: System Configuration Register III (Register 02)
BIT 15 14 NAME Reserved DISPHYReset Reserved (Must set to 0). PHY Reset Option. 0: Reset PHY on link down. 1: Don't reset PHY on link down. Enable skip register 6 read during auto-negotiation for Seeq PHY. 0: Don't skip. 1: Skip Reserved (Must set to 0). Age Resolution. 0: Normal aging. 1: Slow down aging. Backpressure IPG Select Enable. 0: Backpressure IPG = 96BT. 1: According to BpIPGSel value. IPG Control. 0: IPG = 96BT 1: IPG = 64BT Reserved SGRAM Select. 0: 8 Mbit SGRAM 1: 16 Mbit SGRAM Backpressure Control. 0: Carrier based. 1: Collision based. Backpressure IPG Select. 00: 48BT; 01: 56BT; 10: 65BT; 11: 72BT. Reserved 0: Flow control multicast. 1: Flow control multicast/broadcast. DESCRIPTION
13
Skip_Reg6
12~11 10
Reserved AgeRes
9
BpIPGSelEn
8
IPG64
7~6 5
Reserved SG16M
4
BPCOL
3~2 1 0
BpIPGSel Reserved BCdrop_SC
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Reserved Register (Register 03) This register is reserved for Allayers use. The bits should be set as 0000 0001 0001 0100. Testing Register (Register 04) Most of the bits in this register are reserved for factory testing except for the WmarkSel bits. These bits set the level of buffer to trigger backpressure to eliminate buffer overflow.
Table 23: Testing Register (Register 04)
BIT 15~12 11~10 NAME Reserved WmarkSel Reserved Backpressure Watermark Select. 00: Backpressure if available block count < 4. 01: Backpressure if available block count < 8. 10: Backpressure if available block count < 16. 11: Backpressure if available block count < 28 (8 Mbit/s SGRAM). 11: Backpressure if available block count < 60 (16 Mbit/s SGRAM). Each block is 2K byte. Reserved DESCRIPTION
9~0
Reserved
Vendor Specific PHY Register (Register 05) This register is used to program vendor-specific PHY options. It is also used for programming the Vendor Specific PHY register location and bit location of the operation status.
Table 24: Vendor Specific PHY Register (Register 05)
BIT 15 14 13 12~8 7~4 3~0 NAME PHYAD MclkSpd PortOrder PHYOpReg PHYSpBit PHYDxMode DESCRIPTION Setting this bit to "1" will program the MDIO PHY address to 16 to 23. Setting this bit to "1" will reduce the MDIO clock speed to 17 KHz. Setting this bit to "1" will reverse the PHY ID/port number of the switch. PHY's Operation Status Register Number. PHY's Data Rate Status Register Bit Number. PHY's Operating Duplex Mode Status Register Bit Number.
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Table 25: Port Monitoring Configuration (Register 06)
BIT 15 14~10 9~5 4~0 NAME Reserved MdPID MgIPID MgOPID Reserved Monitored Port ID. Snooping Port ID for Incoming Frame Flow. Snooping Port ID for Outgoing Frame Flow. DESCRIPTION
Reserved Registers (Registers 07 to 0C) These registers are reserved and must be set to zero. Port Configuration Registers (Registers 0D to 1C) Registers 0D to 1C are for local port configuration. There are two port configurations per port. Port 0 port configuration uses register 0D and 0E, Port 1 register 0F and 10, etc.
Table 26: Port Configuration Register I
BIT 15~10 NAME UpLinkID DESCRIPTION Uplink ID Associated with the Port. 0XXYYY: Port ID with XX as the device ID and YYY as the port ID. 100XXN: Trunk ID with XX as the device ID and N as the trunk ID. Others: Reserved Trunk Member Port. 0: Individual port. 1: Member of trunk port. Reserved (Set to 0). Broadcast Storm Control Enable. 0: Storm control disable. The broadcast frame will not be throttled. 1: Storm control enable. If the accumulated number of broadcast frames in the input buffer of the port is over the threshold specified in the system configuration register, new incoming broadcast frames will be discarded until the number has been reduced below the threshold. Intrusion Protection. Security control for the frames received from nonuplink ports. 0: Security off. The forwarding decision made about frames received from the port will not involve the source MAC address checking. 1: Security on. The frames received from the port with unknown source MAC address or with source MAC address learned previously from another port will be discarded. Reserved (Set to 0).
9
Tmember
8 7
Reserved StormCTL
6
Security
5
Reserved
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Table 26: Port Configuration Register I (Continued)
4 LrnDis Learning Disable. 0: Source address from this port will be learned. 1: Source address from this port will not be learned. Must set to 11. Reserved (Set to 0).
3~2 1~0
Reserved Reserved
Table 27: Port Configuration Register II
BIT 15~14 13 12 11 10 9~6 NAME Reserved Reserved SkipANDone FlowCtrlFdEn FlowCtrlHdEn MDIOCfg[3:0] Reserved Reserved (Set to 0). Ignore Auto-Negotiation Complete and Wait for Link Up. Flow Control Full-duplex Enable. Flow Control Half-duplex Enable. MDIO Configuration. 0001: Master mode PHY management. 0010: Slave mode PHY management. 0111: Force mode. MDIO Disable. 0: MDIO is enabled. 1: MIDO is disabled. This bit is not relevant when MDIO is enabled. When MDIO is disabled, this bit forces the port into link up or link down state. Force 100 Full-duplex Mode. Force 100 Half-duplex Mode. Force 10 Full-duplex Mode. Force 10 Half-duplex Mode. DESCRIPTION
5
MDIODis
4 3 2 1 0
LinkUp PrtMode100F PrtMode100H PrtMode10F PrtMode10H
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Port VLAN Map Registers (Registers 1E to 2C) These registers provide the VLAN map for each port. Registers 1D, 1F, 21, 23, 25, 27, 29, and 2B are reserved. The values for these reserved registers should be all zero. A VLAN worksheet is provided in Appendix I.
Table 28: Port VLAN Map Registers (Registers 1E to 2C)
BIT 15~8 7 NAME Reserved Port7VLAN Should be set to 0. Port VLAN Corresponding to the Port 7. 0: Non-member port. 1: Member port. Port VLAN Corresponding to the Port 6. 0: Non-member port. 1: Member port. Port VLAN Corresponding to the Port 5. 0: Non-member port. 1: Member port. Port VLAN Corresponding to the Port 4. 0: Non-member port. 1: Member port. Port VLAN Corresponding to the Port 3. 0: Non-member port. 1: Member port. Port VLAN Corresponding to the Port 2. 0: Non-member port. 1: Member port. Port VLAN Corresponding to the Port 1. 0: Non-member port. 1: Member port. Port VLAN Corresponding to the Port 0. 0: Non-member port. 1: Member port. DESCRIPTION
6
Port6VLAN
5
Port5VLAN
4
Port4VLAN
3
Port3VLAN
2
Port2VLAN
1
Port1VLAN
0
Port0VLAN
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Table 29: Miscellaneous Register (Register 2D)
BIT 15~11 10 NAME Reserved L2DASA Set value to 0. Select the Algorithm for MAC Based Loading. 0: SA only. 1: SA and DA. Trunk Link Fail Over. 0: Don't fail-over when a trunk port fails. 1: Allow link fail-over for trunking. Enable 2 or 3 Port MAC Based Trunking Option. 0: Disable 1: Enable MAC Based Trunk Port Mapping for Trunk 1. 0: Non-trunk port. 1: Trunk port. MAC Based Trunk Port Mapping for Trunk 0. 0: Non-trunk port. 1: Trunk port. DESCRIPTION
9
L2Fail
8
L2MAP
7~4
TrunkMap1
3~0
TrunkMap0
Port Trunk Port Assignment Registers (Registers 2E to 35) The Port to Trunk Port assignment register assigns a port to a trunk for port-based load balancing trunking. Please see example in the trunking section. A port to trunk port work sheet is provided in Appendix II.
Table 30: Port Trunk Port Assignment Registers (Registers 2E to 35)
BIT 15~4 3~2 NAME Reserved Trunk1 Should be set to 0. Trunk Port of Trunk 1. 00: Port 4 01: Port 5 10: Port 6 11: Port 7 Trunk Port of Trunk 0. 00: Port 0 01: Port 1 10: Port 2 11: Port 3 DESCRIPTION
1~0
Trunk0
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Table 31: System Status Register (Register 39)
BIT 15 NAME EPTimeOut DESCRIPTION EEPROM Time Out. 0: EEPROM initialized the device. 1: EEPROM is not found. Default configuration. SGRAM Initialization Done. 0: SGRAM initialization is not done. 1: SGRAM initialization is done. SRAM Initialization Done. 0: SRAM initialization is not done. 1: SRAM initialization is done. Register Initialization Done. 0: AL103 register initialization is not done. 1: AL103 register initialization is done. Traffic Counter. 0000: Minimum traffic. 1111: Maximum traffic. Reserved 0101: AL103
14
Sgraminitdone
13
Sraminitdone
12
Reginitdone
11~8
TrafCnt
7~4 3~0
Reserved Version ID
Port Operation Status Registers (Register 3A to 41) Registers 3A to 41 are status indication on a per port basis. These are read only register. Port 0 port status is in register 3A; Port 1 register 3B...and port 7 register 41.
Table 32: Port Operation Status Registers (Register 3A to 41)
BIT 15 NAME LinkFail Port Link Status. 0: Normal 1: Fail Port PHY Status. 0: Normal 1: Error Port Security Violation. 0: Normal 1: Violation DESCRIPTION
14
PHYError
13
Sviolation
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Table 32: Port Operation Status Registers (Register 3A to 41) (Continued)
12 FlowCtrl Flow Control. If port mode ([1:0]) is 2'b01 or 2'b11: 0: Pause disable. 1: Pause enable. If port mode ([1:0]) is 2'b00 or 2'b10: 0: Backpressure based on CRS. 1: Backpressure based on collision. Port Broadcast Storm Status. 0: Normal 1: Stormed Port Input Buffer Full Status. 0: Normal 1: Input buffer full experienced. Table Entry Unavailability for MAC Learning. 0: Normal. 1: Unavailability experienced. Port Jabber Status. 0: Normal 1: Jabber experienced. Port Late Collision Status. 0: Normal 1: Late collision experienced. Port Transmit Pause Status. 0: No transmit pause experienced. 1: Transmit pause experienced. Port Carrier Sense Loss During Transmission Status. 0: No carrier sense loss experienced. 1: Carrier sense loss experienced. False Carrier Status. Transmit Queue Underflow Status. 0: Normal 1: Underflow experienced. Frame Time Out. 0: Normal 1: Frame time out experienced. Port Operating Mode. 00: 10 Mb half-duplex. 01: 10 Mb full-duplex. 10: 100 Mb half-duplex. 11: 100 Mb full-duplex.
11
Stormed
10
InBFull
9
TblUNAVL
8
Jabbered
7
LateCOL
6
TxPaused
5
CRSLoss
4 3
FalseCRS Underflow
2
TimeOut
1~0
PortMode
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Indirect Resource Access Command Register (Register 42) Indirect resource access command allows the management (Reverse EEPROM Method) to access other resources other than the AL103 register values. PHY registers, both internal and external MAC address tables, and SGRAM contents can be accessed using this command.
Table 33: Indirect Resource Access Command Register (Register 42)
BIT 15 NAME CmdDone DESCRIPTION Command Done. 0: Execute new command. 1: Command done. Clear this bit to execute a new command. When finished with the command, the AL103 will set the bit back to "1." Read/Write Operation Command. 0: Read operation. 1: Write operation. Type of Accessed Resource. 000: PHY registers. 001: EEPROM 010: SGRAM 011: MAC address table 1; Read: MAC table address read. Write: MAC address learn. 100: MAC address table 2; Read: MAC address search. Write: MAC address delete. 101-111: Reserved External MAC Address Table Read. If ResType = 011 and Operation = 0 0: On-chip address table read. 1: Off-chip address table read. The Address of the Entry Within the Accessed Resource.
14
Operation
13~11
ResType
10
ExtRD
10~0
ResAddr
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Indirect Resource Access Data Registers Indirect Resource Access Data I through IV is used with indirect resource access command.
Table 34: Indirect Resource Access Data I Register (Register 43)
BIT 15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data 1.
Table 35: Indirect Resource Access Data II Register (Register 44)
BIT 15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data 2.
Table 36: Indirect Resource Access Data III Register (Register 45)
BIT 15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data 3.
Table 37: Indirect Resource Access Data IV Register (Register 46)
BIT 15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data 4.
Table 38: Check Sum (Register 47)
BIT 15~8 7~0 NAME CheckSum Reserved DESCRIPTION Check Sum Value of AL103 Register Contents.
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5. Timing Requirements
Table 39: MII Transmit Timing
SYMBOL ttdv ttxev DESCRIPTION TXCLK to TXD valid time. TXCLK to TXEN valid time. MIN 4 4 TYP MAX 12 12 UNIT ns ns
TXCLK
ttxev ttxev
TXEN
ttdv
TXD
DATA
DATA
DATA
DATA
DATA
DATA
Figure 9
MII Transmit Timing
Table 40: MII Receive Timing
SYMBOL trxds trxdh DESCRIPTION RX_DV, RXD, RX_ER, setup time. RX_DV, RXD, RX_ER hold time. MIN 10 5 TYP MAX UNIT ns ns
RXCLK
trxdh
RXEN
trxds trxdh
RXD
DATA
DATA
DATA
DATA
DATA
DATA
Figure 10
MII Receive Timing
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Table 41: PHY Management (MDIO) Read Timing
SYMBOL tch tcl tmc tms tmh DESCRIPTION MDC high time. MDC low time. MDC period. MDIO setup time. MDIO hold time. MIN 420 420 840 10 10 TYP 425 425 850 MAX 430 430 860 15 UNIT ns ns ns ns ns
MDC
tcl tch
tmc
tms
tmh
MDIO
Figure 11
PHY Management Read Timing
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Table 42: PHY Management (MDIO) Write Timing
SYMBOL tch tcl tmc td DESCRIPTION MDC high time. MDC low time. MDC period. MDIO output delay. MIN 420 420 840 40 TYP 425 425 850 MAX 430 430 860 52 UNIT ns ns ns ns
MDC
tcl tch
tmc
td
MDIO
Figure 12
PHY Management Write Timing
Table 43: SGRAM Refresh Timing
SYMBOL tAH tAS tCH tCHI tCK tCKH tCKS tCL tCS tRP tRC DESCRIPTION Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. CKE hold time. CKE setup time. Clock low level width. PBCS#, PBRAS#, PBWE# setup time. Precharge command period. Auto-refresh to auto-refresh period. MIN 1 3 1 3.5 10 1 3 3.5 3 30 90 TYP MAX UNIT ns ns ns ns ns ns ns ns ns ns ns
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PBCLK tCKS tCKH
tCK
tCHI
tCL
CKE tCS tCH
Command
Precharge
NOP
Auto Refresh
NOP
Auto Refresh
NOP
Active
BANK
BANK ROW
Address
tRP
Don't Care
tRC
tRC
Figure 13
SGRAM Refresh Timing
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Table 44: SGRAM Read Timing
SYMBOL tAC tAH tAS tCH tCHI tCK tCKH tCKS tCL tCS tHZ tLZ tOH tRAS tRCD DESCRIPTION Access time. Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. CKE hold time. CKE setup time. Clock low level width. PBCS#, PBRAS#, PBWE# setup time. Data out high impedance time. Data out low impedance time. Data out hold time. Active to precharge command period. Active to read delay. MIN 2 2.5 1 3 13 2 3 3 2.5 2 2 48 24 TYP MAX 10 8 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: This timing requirement is for a SGRAM running at CAS Latency 2. Typically a -8 speed grade SGRAM needs to be used.
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tCK
tCL
tCHI
PBCLK
tCKS
tCKH
CKE tCS tCH BURST TERM.
Command
Active
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
A0-A7
ROW
column m
A8 tAS PBBA
ROW tAH BANK 0 BANK 0
tAC tAC tOH
PBD tLZ tRCD (Bank 0) CAS Latency
Dout m
Dout m+1
Dout m+2
Dout m-1
Dout m
Dout m+1
256 location within the same row
tHZ
tRAS (Bank 0)
Figure 14
SGRAM Read Timing
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Table 45: SGRAM Write Timing
SYMBOL tAH tAS tCH tCHI tCK tCKH tCKS tCL tCS tDH tDS tRAS tRCD DESCRIPTION Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. CKE hold time. CKE setup time. Clock low level width. PBCS#, PBRAS#, PBWE# setup time. Data in hold time. Data in setup time. Active to precharge command period. Active to read delay. MIN 2 2.5 1 3 13 2 3 3 2.5 1 2.5 48 24 TYP MAX 100,000 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: This timing requirement is for a SGRAM running at CAS Latency 2. Typically a -8 speed grade SGRAM needs to be used.
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tCK
tCHI
PBCLK
tCKS
tCKH
tCL
CKE tCS tCH Command Active NOP write NOP NOP NOP NOP NOP BURST TERM. NOP
A0-A7
ROW
column m
A8
ROW tAS tAH BANK 0
PBBA
BANK 0
tDS
tDH
PBD
Din m
Din m+1
Din m+2
Din m+3
Din m-1
Din m
tRCD (Bank 0) tRAS (Bank 0)
Don't Care 256 location within the same row Undefined
Figure 15
SGRAM Write Timing
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6. Electrical Specifications
Note: Operation at absolute maximum ratings for an extended period of time could cause permanent damage to the device.
Table 46: Maximum Ratings
DC Supply Voltage (Vcc) DC Input Voltage DC Output Voltage DC Supply Voltage to MII DC Input Voltage to MII DC Output Voltage to MII Storage Temperature -0.3V ~ + 3.6V -0.3 ~ Vcc + 0.3V -0.3 ~ Vcc + 0.3V -0.6V to 6.0V -0.6 to Vcc5 + 0.3V -0.6 to Vcc5 + 0.3V -55 oC to +150 oC
Table 47: Recommended Operation Conditions
Supply Voltage Operating Temperature Power Dissipation 3.3V 0.3V 0 oC to 70 oC 1.7 W (typical)
Table 48: DC Electrical Characteristics
PARAMETER Voh Vol Ioz Iih Iil Vih Vil Icc DESCRIPTION Output voltage-high, Ioh=4mA Output voltage-low, Ioh=4mA High impedance state output current Input current-high (With no pull-up or pull-down) Input current-low (With no pull-up or pull-down) Input high voltage Input low voltage Supply current MIN 2.4 -10 -10 -10 0.7*Vcc TYP MAX 0.4 10 10 10 0.3*Vcc UNIT V V uA uA uA V V mA
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7. AL103 Mechanical Data
256 PQFP Package
25.2
0.18 0.04
0.40
28.00 0.10 30.6 0.15
3.23 0.07
4.07 max. 0.60 0.10 0.25 1.30 0.10
0.35 0.10 0.25 min.
Figure 16
AL103 Mechanical Dimensions
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AL103 Revision 1.0
8. Appendix I (VLAN Mapping Worksheet)
PORT 6/REG. 2A
PORT
BIT
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
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PORT 7/REG. 2C
PORT 0/REG. 1E
PORT 1/REG. 20
PORT 2/REG. 22
PORT 3/REG. 24
PORT 4/REG. 26
PORT 5/REG. 28
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AL103 Revision 1.0
9. Appendix II (Port to Trunk Port Assignment Work Sheet)
PORT 0/REG. 2E
PORT 1/REG. 2F
PORT 2/REG. 30
PORT 3/REG. 31
PORT 4/REG. 32
PORT 5/REG. 33
PORT 6/REG. 34
TRUNK / PORT
BIT/ VALUE
7 TRUNK 1 BITS 3, 2 6 5 4 3 TRUNK 0 BITS 1, 0 2 1 0
11 10 01 00 11 10 01 00
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PORT 7/REG. 35 62
AL103 Revision 1.0
10. Appendix III (Suggested Memory Components)
Note: This is only a partial list of memory components that can be used in Allure devices. The AL103 uses Frame Buffer SGRAM chips that require 32-bit wide SGRAM or SDRAM, that is 80 MHz or faster with CAS latency 2. The following lists some of the memory that can be used in the AL103.
DEVICE
FREQ.
8 Mbit SGRAM
16 Mbit SGRAM
AL103
80 MHz
MoSys - MG802C256Q-10 Etron - EM635327Q-8
MoSys - MG802C512L-8 Etron - EM636327Q-8 Winbond - W971632AF-7 Oki - MS82V16520-7
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AL103 Revision 1.0
Rev. History (Prelim. 1.1 to 1.1a) 1. Reformatted and edited document. 2. Added AL103 overview. 3. Added memory information in appendix III. 4. Added new PHY management timing diagrams. 5. Added new RMII and MII timing diagrams. Rev. History (Prelim. 1.1a to 1.2) 1. Changed bits 11~15 to reserved in the Miscellaneous Register, Table 29. 2. Revised Queue Management (3.9) section. Prelim. 1.2 to Rev. 1.0 1. Fully released document.
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Index
A Address Aging 19 Address Learning 19 AL103 Interface Block Diagram 15 AL103 Overview 5 AL103 Pin Diagram (Top View) 6 Appendix I (VLAN Mapping Worksheet) 61 Appendix II (Port to Trunk Port Assignment Work Sheet) 62 Appendix III (Suggested Memory Components) 63 B Broadcast Storm Control 17 C Check Sum (Register 47) 50 D Data Reception 16 DC Electrical Characteristics 59 E EEPROM Interface 13, 29 EEPROM Map 32 EEPROM Read Cycle 31 EEPROM Start and Stop Bit 30 EEPROM Write Cycle 30 F False Carrier Events 16 Flow Control 25 Frame Filtering 16 Frame Forwarding 17 Frame Generation 18 Frame Transmission 18 Full Duplex Flow Control (802.3X) 26 Functional Description 16 H Half Duplex Flow Control (Backpressure) 25 Half Duplex Mode Operation 18 I Illegal Frame Length 16 Indirect Resource Access Command Register (Register 42) 49 Indirect Resource Access Data I Register (Register 43) 50 Indirect Resource Access Data II Register (Register 44) 50 Indirect Resource Access Data III Register (Register 45) 50 Indirect Resource Access Data IV Register (Register 46) 50 L Load Balancing 21 Long Frames 16 M MAC Based Load Balancing Set Up 24 Maximum Ratings 59 Media Independent Interface (MII) 28 MII Interface Port 0 7 MII Interface Port 1 7 MII Interface Port 2 8 MII Interface Port 3 9 MII Interface Port 4 9 MII Interface Port 5 10 MII Interface Port 6 10 MII Interface Port 7 11 MII PHY Management Interface 13 MII Receive Timing 51 MII Transmit Timing 51 Miscellaneous Pins 14 Miscellaneous Register (Register 2D) 46 N Non Auto-negotiation Mode 29 O Other PHY Options 29 P PHY Management 28 PHY Management (MDIO) Read Timing 52 PHY Management (MDIO) Write Timing 53 PHY Management Master Mode 28 PHY Management MDIO 28 PHY Management Slave Mode 28 Pin Descriptions 7 Port Aggregation 21 Port Based Trunk Load Balancing 22 Port Configuration Register II 44 Port Configuration Registers (Registers 0D to 1C) 43 Port Monitoring 27 Port Monitoring Configuration (Register 06) 43 Port Operation Status Registers (Register 3A to 41) 47 Port Trunk Port Assignment Registers (Registers 2E to 35) 46 Port VLAN Map Registers (Registers 1E to 2C) 45 Power Interface 14 Product Description 1 Q Queue Management 26 R Recommended Operation Conditions 59 Register Tables Summary 36 Reprogramming the EEPROM Configuration 31 Reserved Register (Register 03) 42 Reserved Registers (Registers 07 to 0C) 43 S Secure Mode Operation 18 SGRAM Interface 12, 36 SGRAM Read Timing 55 SGRAM Refresh Timing 53 SGRAM Write Timing 57 Static Address Entry Format for EEPROM 32 System Block Diagram 1 System Configuration Register I (Register 00) 39 System Configuration Register II (Register 01) 40 System Configuration Register III (Register 02) 41 System Initialization 29
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AL103 Revision 1.0
System Status Register (Register 39) 47 T Testing Register (Register 04) 42 Trunk Fail Over 21 Trunk Port Assignment 22 Trunk Port Numbering 22 U Uplink Port 27 V Vendor Specific PHY register (Register 05) 42 VLAN Map for an 8 Port Switch 20 VLAN Mapping for Port Based Load Balancing Trunk 23 VLAN Support 19
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